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A microprocessor is clocked at a rate of 20 GHz. a. How long

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1. A microprocessor is clocked at a rate of 20 GHz.;a. How long is a clock cycle?;b. What is the duration of a particular type of machine instruction consisting of six clock cycles?;Answers to problem 1 should be in nanoseconds;2. A microprocessor provides an instruction capable of moving a string of bytes from one area of memory to another. The fetching and initial decoding of the instruction takes 10 clock cycles. Thereafter, it takes 15 clock cycles to transfer each byte. The microprocessor is clocked at a rate of 10 GHz.;a. Determine the length of the instruction cycle for the case of a string of 64 bytes.;b. What is the worst-case delay for acknowledging an interrupt if the instruction is non-interruptible?;c. What is the worse-case delay for acknowledging an interrupt if the instruction can be interrupted at the beginning of each byte transfer?;Answers to problem 2 should be in nanoseconds;3. Consider the timing diagram of Figure 14.10. Assume that there is only a two-stage pipeline (fetch, execute). Redraw the diagram to show how many time units are now required for six instructions.;4. A pipelined processor has a clock rate of 8 GHz and executes a program with 1.5 million instructions. The pipeline has five stages and instructions are issued at a rate of one per clock cycle. Ignore penalties due to branch instruction and out-of-sequence executions.;a. What is the speedup of this processor for this program compared to a non-pipelined processor, making the same assumptions used in Section 14.4?;b. What is the throughput of the pipelined processor?;5. a. What are some typical distinguishing characteristics of RISC organization?;b. Briefly explain the two basic approaches used to minimize register-memory operations on RISC machines.;6. a. What is the essential characteristic of the superscalar approach to processor design?;b. What is the difference between the superscalar and superpipelined approaches?;For problems 7 through 9, consider a CPU that implements four parallel fetch-execute pipelines for superscalar processing. Show the performance improvement over scalar pipeline processing and no-pipeline processing, assuming an instruction cycle similar to figure 4.1 in the commentary, i.e.;? a one clock cycle fetch;? a one clock cycle decode;? a two clock cycle execute;and a 60 instruction sequence;7. (12 points)?o pipelining would require _____ clock cycles;8. (12 points) A scalar pipeline would require _____ clock cycles;9. (12 points) A superscalar pipeline with four parallel units would require ______ clock cycles

 

Paper#17543 | Written in 18-Jul-2015

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