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ECET-230 ? Digital Circuits and Systems week six assignment

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ECET-230 ? Digital Circuits and Systems;Homework Assignment #6;Name;1. The group of bits 10110101 is serially shifted (right-most bit first) into an 8-bit shift register with an initial state of 11100100. After two clock pulses, the register contains;(a) 01011110 (b) 10110101 (c) 01111001 (d) 00101101;1. With a 100 kHz clock frequency, eight bits can be serially entered into a shift register in;(a) 80 m s (b) 8 m s (c) 80 ms (d) 10 m s;1.;Data out;CLK;Data in;D SRG 10;C;For a 10-bit serial-in/serial-out shift register, determine Data out for the Data in and clock waveforms shown below. Assume that the register is initially cleared.;1. Using Quartus II, or an equivalent VHDL entry program, develop the text file and simulation for the shift register specified in Problem 3. Verify the timing diagram shown in Problem 3. Attach the.vhd and simulation files.;Solution;1. Using Quartus II, or an equivalent VHDL entry program, develop the text file and simulation for the 74LS194A universal, bi-directional shift register. Attach the.vhd and simulation files.;1. In your own words, explain the purpose of concatenation in a VHDL signal assignment.;1. Develop the state diagram for a MOD-4 counter with an even number count sequence: 000, 010, 100, 110, 000, etc. All undefined states must return to 000.;1. Develop the text file for the counter specified in Problem 7 using state types.;1. Modify the text file from Problem 8 so that the counter only counts odd numbers: 001, 011, 101, 111, 001, etc.;In your own words, explain the difference between Mealy and Moore machines

 

Paper#66910 | Written in 18-Jul-2015

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