Part A) Required: Design and simulate a decimal counter using the VHDL test bench file genericclocktest.vhw above. Design and simulate your...
Part A) Required: Design and simulate a decimal counter using the VHDL test bench file genericclocktest.vhw above. Design and simulate your decimal (BCD) counter schematic in a separate project. You should then load and test each of your labs 2, 3 and BCD counter schematic designs in the logic board by themselves. Then create a new, hierarchical project design. First create a top level schematic. You could start from the "wires" project, and add schematics to the design by using the "add source" in ISE. Then use the design utility to make each of the designs into a schematic symbol. The top level schematic will be your block diagram, and each block will be the symbol corresponding to a given schematic. Once your BCD counter simulation is working, add the BCD to seven segment decoder from lab #2 to this project to display the count on the seven segment LED: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5... You can test your counter using the 2Hz clock from the clock divider in the HelloWorld project to drive the clock input of your decimal counter. The final part of the Lab 4 design will be your BCD counter feeding your BCD to Red ID converter feeding your BCD to seven segment decoder. When the combination runs in the board, it will display your Red ID number continuously, one digit at a time.
Paper#68723 | Written in 18-Jul-2015Price : $27