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##### Module 2 Combinational Logic, Storage Elements and Finite State Machines Lab

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Part 1;The circuit below implements the basic RS latch.;(a) Analyze the circuit and draw a detailed timing diagram. Assume that there is a delay of five time units for;each gate and that Q output and the R and S are initially 0. Base your analysis on the following input;sequence: (R,S) = (0,0),(01),(0,0),(1,0),and (0,0).;(b) Repeat the analysis, using the min?typical or typical?max delay ranges from the vendor?s data sheets for;the parts you are using.;(c) Verify your analysis using a Verilog structural model for the circuit and the vendor?s data sheets.;Part 2;The goal is to design and implement a high?speed logical shifter. The specification you have been given;requires the design of a circuit that will shift a 16?bit word to the right or to the left by 1?,2?,3?, or 4?bit;positions in a single clock time.;The input to your system is a 3?bit word that is to be interpreted as follows;B2? 0 shift right;1 shift left;B1;B0;Meaning;0;0;Shift by 1;0;1;Shift by 2;1;0;Shift by 3;1;1;Shift by 4;(a) Draw a top?level block diagram for your system.;(b) Assume you decide to build the shifter using 16 D flip?flops. Write the logic equations for the D inputs.;(c) Explain how your design works.;(d) Confirm your design by writing and testing a structural Verilog model.

Paper#72001 | Written in 18-Jul-2015

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